Three-dimensional wafer bonding, or wafer stacking, is the bonding together of two or more semiconductor wafers upon which integrated circuitry has been formed. The wafer stack that is formed is subsequently diced into separate stacked die, each stacked die having multiple layers of integrated circuitry. Wafer stacking may offer a number of potential benefits. For example, integrated circuit (IC) devices formed by wafer stacking may provide enhanced performance and functionality while perhaps lowering costs and improving form factors. System-on-chip (SOC) architectures formed by wafer stacking can enable high bandwidth connectivity between stacked die with dissimilar technologies—e.g., logic circuitry and dynamic random access memory (DRAM)—that otherwise have incompatible process flows. Also, by using three-dimensional wafer bonding, smaller die sizes may be achieved, which can reduce interconnect delays. There are many potential applications for wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, the aforementioned SOC solutions, as well as others.
One method for three-dimensional wafer bonding is metallic bonding. In metallic wafer bonding, two wafers are joined by bonding metal bond structures formed on one of the wafers with corresponding metal bond structures formed on the other wafer. For example, a number of copper bond pads may be formed on a first wafer and a corresponding number of copper bond pads may be formed on a second wafer. The first and second wafers are aligned and brought together, such that each of the copper pads on the first wafer mates with a corresponding one of the copper pads on the second wafer. A bonding process is then performed (e.g., as by application of pressure and/or elevated temperature) to join the mating bond pads, thereby forming a plurality of interconnects between the first and second wafers, which now form a wafer stack. Each of the first and second wafers includes integrated circuitry for a plurality of die, and the wafer stack is cut into a number of stacked die. Each stacked die comprises one die from the first wafer and another die from the second wafer, these die being mechanically and electrically coupled by some of the previously formed interconnects.